IBM is seeking a long-term partnership with Japan’s Rapidus to develop sub-1nm chips, according to Yomiuri Shimbun. Building on their 2nm collaboration, IBM has deployed engineers to Rapidus’s Hokkaido site, signaling deeper ties as both companies pursue next-generation semiconductor production and Japan ramps up investment in chip innovation.
According to the report, Mukesh Khare, General Manager of IBM’s semiconductor R&D division, expressed IBM’s intention to build a long-term partnership with Rapidus to advance next-generation semiconductor technologies. In addition to ongoing collaboration on 2nm chip mass production, IBM hopes to continue working with Rapidus on even more advanced process nodes.
The report noted that IBM aims to develop sub-1nm semiconductor technology within the next few years, and Rapidus may take on the task of mass production for these chips in the future. Khare confirmed that IBM has dispatched about 10 engineers to Rapidus’s facility in Hokkaido and emphasized the company’s full support to help Rapidus achieve successful 2nm chip production by 2027.
IBM and Japanese semiconductor firm Rapidus have expanded their collaboration to develop mass-production technologies, with a focus on 2nm-generation semiconductors. The partnership, announced in June 2024, supports Japan’s New Energy and Industrial Technology Development Organization (NEDO) project aimed at advancing chiplet and package design for next-generation semiconductors.
By December 2024, the collaboration reached a notable milestone with the creation of a new chip construction method called selective layer reductions. This process enables the consistent production of nanosheet gate-all-around transistors with multiple threshold voltages (multi-Vt). The innovation facilitates more energy-efficient and complex computations, which are crucial for scaling 2nm transistors to mass production levels.
Article edited by Jack Wu